History Of VLSI Coding
The expression for this method was "Automated Integrated Design Systems" (later renamed to Gateway Automation in 1985) as a hardware modeling language. Gateway Automation was purchased by Cadence Design Systems in 1990. Cadence currently has full proprietary rights to Gateway's Verilog and also the Verilog-XL, the HDL-simulator that will become the actual commonplace (of Verilog logic simulators) for consecutive decade. Originally, Verilog was supposed to explain and permit simulation; solely later on was support for synthesis additional.
Verilog-95
With
the increasing success of VHDL at the time, Cadence determined to
create the language obtainable for open standardization. Cadence
transferred Verilog into the general public domain beneath the Open
Verilog International (OVI) (now referred to as Accellera)
organization. Verilog was later submitted to IEEE and have become
IEEE normal 1364-1995, unremarkably cited as Verilog-95.
In
the same timeframe Cadence initiated the creation of Verilog-A to
place standards support behind its analog machine Spectre. Verilog-A
was never supposed to be a standalone language and could be a set of
Verilog-AMS that encompassed Verilog-95.
.
Verilog
2001
Extensions
to Verilog-95 were submitted back to IEEE to cover the deficiencies that users
had found in the original Verilog standard. These extensions became IEEE Standard
1364-2001 known as Verilog-2001.
Verilog-2001
is a significant upgrade from Verilog-95. First, it adds explicit support for
(2's complement) signed nets and variables. Previously, code authors had to
perform signed operations using awkward bit-level manipulations (for example,
the carry-out bit of a simple 8-bit addition required an explicit description
of the Boolean algebra to determine its correct value). The same function under
Verilog-2001 can be more succinctly described by one of the built-in operators:
+, -, /, *, >>>. A generate/endgenerate construct (similar to VHDL's
generate/endgenerate) allows Verilog-2001 to control instance and statement
instantiation through normal decision operators (case/if/else). Using
generate/endgenerate, Verilog-2001 can instantiate an array of instances, with
control over the connectivity of the individual instances. File I/O has been
improved by several new system tasks. And finally, a few syntax additions were
introduced to improve code readability (e.g. always @*, named parameter
override, C-style function/task/module header declaration).
Verilog-2001
is the dominant flavor of Verilog supported by the majority of commercial EDA software
packages.
Categories:
0 comments:
Post a Comment